1. Field of the Invention
The present invention generally relates to a memory device and a test method thereof, and more specifically, to a technology of verifying failure of a cell region by intercepting a bit line connected to the cell region in a write-verify-read test performed to verify a normal operation of peripheral circuits other than the cell region.
2. Description of the Prior Art
Generally, operation modes supported by an integrated circuit device or a memory device include a user mode supported for users and a test mode for analysis of operation characteristics of a chip by a chip maker.
FIG. 1 is a block diagram illustrating a conventional memory device.
The conventional memory device comprises a cell array block 2, a bit line sense amplifier 4, a bit line switch 6 and a peripheral circuit 8. Also, the memory device comprises a plurality of bit lines BL0˜BLn, a dummy bit line BLD set as a bit line precharge voltage VBLP, and a dummy sub word line SWLD set as a ground voltage VSS.
The cell array 2 includes a plurality of memory cells (not shown) arranged in a matrix and a plurality of sub word lines SWLL and SWLR.
The bit line sense amplifier 4 senses and amplifies data in the bit lines BL0˜BLn.
The bit line switch 6 selectively separates the bit lines BL0˜BLn of the bit line sense amplifier 4 from those of the cell array 2 in response to separation control signals SHLB and SHRB.
The peripheral circuit 8 externally outputs data amplified by the bit line sense amplifier 4 through an input/output bus IOBUS or transmits externally inputted data to the bit line sense amplifier 4.
When a write-verify-read test is performed on the above-described memory device, all of the cell array 2, the bit line sense amplifier 4 and the peripheral circuit 8 (A in FIG. 1) are operated in the same way as in a normal operation.
Here, the bit line switch 6 connects the bit lines BL0˜BLn of the bit line sense amplifier 4 to those of the selected cell array.
If the bit lines BL0˜BLn of the bit line sense amplifier 4 are not separated from those of the cell array 2 when the bit lines BL0˜BLn connected to the cell array 2 and the bit line sense amplifier 4 are connected with other lines, for example, a ground line GND or other nodes than a drain of a cell transistor (not shown) to cause failure, the same failure is represented in the cell array 2, so that failure of the peripheral circuit 8 and the bit line sense amplifier 4 cannot be verified.
When the main bit lines BL0˜BLn and a dummy bit line BLD are connected to dummy word lines WLLD and SWRD set at a ground level VSS (short), the bit line switches 4 should all be turned off for verification of the connection state. However, it is impossible to turn off all bit line switches 4 in a common memory device.